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CXD1915R
Digital Video Encoder
Description The CXD1915R is a digital video encoder designed for DVDs, set top boxes, digital VCRs and other digital video equipment. This device accepts ITUR601 format Y, Cb and Cr data and ITU-R656 format Y, Cb and Cr data, and the data are encoded to composite video and separate Y/C video (S-video) signals and converted to RGB/YUV signals. Features * NTSC, PAL, MPAL and 4.43NTSC encoding modes * Composite video and separate Y/C video (S-video) signal output * R, G, B/Y, U, V (BetaCam/SMPTE level) signal output * 8/16-bit pixel data input modes * 13.5Mpps pixel rate * 12.27 and 14.75Mpps square pixel rates * External synchronization using HSYNC, VSYNC and FID inputs, or internal synchronization * Supports interlace and non-interlace modes * On-chip 100% color bar generator * OSD function * ITU-R656 code signal EAV decoding * Supports I2C bus (400kHz) and Sony SIO * Closed Caption (line 21, line 284) encoding * VBID encoding * WSS encoding * 10-bit 6-channel DAC * Macrovision Pay-Per-View copy protection system Rev. 7.1.L11 * Monolithic CMOS single 3.3V power supply * 80-pin plastic LQFP 80 pin LQFP (Plastic)
Absolute Maximum Ratings * Supply voltage VDD VSS - 0.5 to +4.6 V * Input voltage VI VSS - 0.5 to +7.0 V * Output voltage VO VSS - 0.5 to VDD + 0.5 V * Operating temperature Topr -20 to +75 C * Storage temperature Tstg -55 to +150 C (VSS = 0V) Recommended Operating Conditions * Supply voltage VDD 3.3 0.3 * Input voltage VIN VSS to 5.5 * Operating temperature Topr 0 to +70 I/O Capacitance * Input capacitance CI * Output capacitance CO
V V C
9 (Max.) 11 (Max.)
pF pF
Note) Test conditions: VDD = VI = 0V, fM = 1MHz
1 This device is protected by U.S. patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. Use of the Macrovision anticopy process in the device is licensed by Macrovision for non-commercial home use only. Reverse engineering or disassembly is prohibited. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E99422-PS
Block Diagram
PD0 to 7 YUV/RGB translator Interpolater Y Delay LPF Modulator LPF Interpolater CROMA 10bit DAC U V 10bit DAC 56
22 to 25, 27 to 30 10bit DAC 59
R/V-OUT G/Y-OUT
PD8 to 15
32 to 35, 37 to 40 Y, U, V Selector Y, U, V
PIXCON 73
Demultiplex, Level translator and Interpolator 4:2:2 to 4:4:4
54 B/U-OUT
XRST 12
ROSD 68
10bit DAC 10bit DAC 10bit DAC
45 51
CP-OUT Y-OUT
GOSD 69
OSD Gen.
BOSD 70
OSDSW 67
48 C-OUT VG 50
FID 16
VSYNC 17 BURST FLAG CSYNC SYNC Slope Gen.
-2-
Sub Carrier Gen. Closed Caption Encoder (for NTSC) MACRO VISION Signal Gen. Internal CLK VBID & WSS Gen.
HSYNC 18
CSYNC 19
43 44 49 75 76 77 78 79
IREF VREF VB TDI TMS TDO TCK TRST 61 TVSYNC 62 to 64 TD8 to 10 66 XTEST CXD1915R 71 XTEST5
BF 20
SYNC Gen. and Timing Controller
F1
1
XVRST
2
SYNCM 72
XIICEN
3
XCS/SA
4
SI/SDA
5
I2C Bus and SIO Controller
SO
6
SCK/SCL
8
PDCLK
14
1/2
SYSCLK
10
CXD1915R
Pin Description Pin No. Symbol I/O Description Field ID input. This signal indicates the field ID when resetting the vertical sync. High indicates 1st field. Low indicates 2nd field. Vertical sync reset input in active Low. This pin is pulled up. This is used for synchronizing the phases of the external and internal vertical sync signals. When XVRST = Low, the internal digital sync generator is reset according to the F1 status. Serial interface mode select input. This pin is pulled up. When XIICEN = Low, Pins 4, 5, 6 and 8 are I2C bus mode. When XIICEN = High, Pins 4, 5, 6 and 8 are Sony SIO mode. This pin's function is selected by XIICEN (Pin 3). This pin is pulled up. When XIICEN = High, this pin is Sony SIO mode; XCS chip select input. When XIICEN = Low, this pin is I2C bus mode; SA slave address select input signal which selects the I2C bus slave address. This pin's function is selected by XIICEN (Pin 3). When XIICEN = High, this pin is Sony SIO mode; SI serial data input. When XIICEN = Low, this pin is I2C bus mode; SDA input/output. This pin's function is selected by XIICEN (Pin 3). When XIICEN = High, this pin is Sony SIO mode; SO serial output. When XIICEN = Low, this pin is not used and output is high impedance. Digital ground. This pin's function is selected by XIICEN (Pin 3). When XIICEN = High, this pin is Sony SIO mode; SCK serial clock input. When XIICEN = Low, this pin is I2C bus mode; SCL input. Digital ground. System clock input. To generate the correct subcarrier frequency, precise 27MHz is required. Digital ground. System reset input in active Low. Set to Low for 40 clocks (SYSCLK) or more during power-on reset. Digital ground. Pixel data clock signal output for 13.5MHz. A 13.5MHz signal frequency divided from the system clock (SYSCLK) is output and used as the clock signal when 16-bit pixel data is input. Digital power supply. Field ID input/output. When SYNCM (Pin 72) = High, the CXD1915R is set to master mode and outputs as follows. When control register bit "FIDS" = "1": Low indicates 1st field and High indicates 2nd field. When control register bit "FIDS" = "0": High indicates 1st field and Low indicates 2nd field. When SYNCM (Pin 72) = Low, the CXD1915R is set to slave mode and this pin becomes the field ID input. -3-
1
F1
I
2
XVRST
I
3
XIICEN
I
4
XCS/SA
I
5
SI/SDA
I/O
6 7 8 9 10 11 12 13 14 15
SO VSS1 SCK/SCL VSS2 SYSCLK VSS3 XRST VSS4 PDCLK VDD1
O -- I -- I -- I -- O --
16
FID
I/O
CXD1915R
Pin No.
Symbol
I/O
Description Vertical sync signal input/output. When SYNCM (Pin 72) = High, this pin is the vertical sync signal output. When SYNCM = Low, this pin is the vertical sync signal input, and the falling edge is detected during the 1st field to reset the internal circuits. Horizontal sync signal input/output. When SYNCM (Pin 72) = High, this pin is the horizontal sync signal output. When SYNCM = Low, this pin is the horizontal sync signal input, and the falling edge is detected during the 1st field to reset the internal circuits. Composite sync output when using RGB output. Burst flag output. The burst flag is synchronized with the composite video signal (CP-OUT) and indicates its color burst signal position. Digital ground. 8-bit pixel data inputs, or lower 8-bit pixel data inputs when 16-bit pixel data is input. [PD0 to PD7] When control register bit "PIF MODE" = "0", these are multiplexed Y, Cb, and Cr signal inputs. When control register bit "PIF MODE" = "1", these are Y signal inputs. Digital power supply. 8-bit pixel data inputs, or lower 8-bit pixel data inputs when 16-bit pixel data is input. [PD0 to PD7] When control register bit "PIF MODE" = "0", these are multiplexed Y, Cb, and Cr signal inputs. When control register bit "PIF MODE" = "1", these are Y signal inputs. Digital ground. Upper 8-bit pixel data inputs when 16-bit pixel data is input/test data bus. [PD8 to PD15] When control register bit "PIF MODE" = "0", these inputs are not used. When control register bit "PIF MODE" = "1", these are multiplexed Cb and Cr signal inputs. In test mode, these are used for the internal circuit test data bus. The test data bus is available only for the device vendor. Digital ground. Upper 8-bit pixel data inputs when 16-bit pixel data is input/test data bus. [PD8 to PD15] When control register bit "PIF MODE" = "0", these inputs are not used. When control register bit "PIF MODE" = "1", these are multiplexed Cb and Cr signal inputs. In test mode, these are used for the internal circuit test data bus. The test data bus is available only for the device vendor. Digital power supply. Not connected inside the IC. DAC reference current output. Connect resistance "16R" which is 16 times output resistance "R". DAC reference voltage input. Sets the DAC output full-scale width. 10-bit DAC output. This pin outputs the composite signal. -4-
17
VSYNC
I/O
18
HSYNC
I/O
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
CSYNC BF VSS5 PD0 PD1 PD2 PD3 VDD2 PD4 PD5 PD6 PD7 VSS6 PD8/TD0 PD9/TD1 PD10/TD2 PD11/TD3 VSS7 PD12/TD4 PD13/TD5 PD14/TD6 PD15/TD7 VDD3 NC IREF VREF CP-OUT
O O -- I I I I -- I I I I -- I/O I/O I/O I/O -- I/O I/O I/O I/O -- -- O I O
CXD1915R
Pin No. 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Symbol AVDD1 AVSS1 C-OUT VB VG Y-OUT AVDD2 AVSS2 B-OUT AVSS4 G-OUT AVDD3 AVSS3 R-OUT VSS8 TVSYNC TD8 TD9 TD10 VDD4 XTEST OSDSW/ XTEST1 ROSD/ XTEST2 GOSD/ XTEST3 BOSD/ XTEST4 XTEST5 SYNCM
I/O -- -- O O O O -- -- O -- O -- -- O -- I I/O I/O I/O -- I I I I I I I Analog power supply. Analog ground.
Description
10-bit DAC output. This pin outputs the chroma (C) signal. Connect to ground via a capacitor of approximately 0.1F. Connect to analog power supply via a capacitor of approximately 0.1F. 10-bit DAC output. This pin outputs the luminance (Y) signal. Analog power supply. Analog ground. 10-bit DAC output. This pin outputs the B and U signals. Analog ground. 10-bit DAC output. This pin outputs the G and Y signals. Analog power supply. Analog ground. 10-bit DAC output. This pin outputs the R and V signals. Digital ground. Test pin. This pin is pulled up. Normally this pin should be open. Test data inputs/outputs. These pins should be open. In test mode, these are used for the internal circuit test data bus. The test data bus is available only for the device vendor. Digital power supply. Test mode control. This pin is pulled up. Normally this pin should be open.
These pins are pulled up. The functions of these pins are selected by XTEST (Pin 66). When XTEST = High, these are OSD data inputs. When XTEST = Low, these are test mode control inputs. The test mode is available only for the device vendor.
Test pin. This pin is pulled up. Normally this pin should be open. Master/slave switching. This pin is pulled up. When SYNCM = High, the CXD1915R is set to master mode. When SYNCM = Low, the CXD1915R is set to slave mode. Control register bit "PIX_EN" default value control. This pin is pulled up. Digital ground. Test mode control input. This pin is pulled up. -5-
73 74 75
PIXCON VSS9 TDI
I -- I
CXD1915R
Pin No. 76 77 78 79 80
Symbol TMS TDO TCK TRST VDD5
I/O I O I I --
Description Test mode control input. This pin is pulled up. Test output. This pin should be open. Test mode control input. Fix to High. Test mode reset input. Set to Low for 40 clocks (SYSCLK) or more during poweron reset. Digital power supply.
-6-
CXD1915R
Electrical Characteristics DC Characteristics Item Input High voltage Input Low voltage Input High voltage Input Low voltage Output High voltage Output Low voltage Output High voltage Output Low voltage Output High voltage Output Low voltage Input leak current Input leak current Supply current Symbol VIH1 VIL1 VIH2 VIL2 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 IIL1 II2 IDD Measurement conditions VDD = 3.3 0.3V VDD = 3.3 0.3V VDD = 3.3 0.3V VDD = 3.3 0.3V IOH = -8.0mA VDD = 3.3 0.3V IOL = 8.0mA VDD = 3.3 0.3V IOH = -4.0mA VDD = 3.3 0.3V IOL = 4.0mA VDD = 3.3 0.3V IOH = -2.0mA VDD = 3.3 0.3V IOL = 4.0mA VDD = 3.3 0.3V VI = 0V VDD = 3.3 0.3V VI = 0 to 5.5V VDD = 3.3 0.3V VDD = 3.3 0.3V -240 -40 -100 2.4 0.4 -40 40 359 VDD - 0.4 0.4 VDD - 0.4 0.4 0.7VDD Min. 0.7VDD Typ. Max. 8 0.2VDD 8 0.3VDD (Ta = 0 to +70C, VSS = 0V) Unit V V V V V V V V V V A A mA Measurement pins 1 1 2 2 3 3 4 4 5 5 6 7
Notes: 1 F1, XVRST, XIICEN, XCS/SA, SYSCLK, XRST, FID, VSYNC, HSYNC, PD0 to PD15, TVSYNC, TD8 to TD10, XTEST, OSDSW, ROSD, GOSD, BOSD, XTEST5, SYNCM, PIXCON, TDI, TMS, TCK, TRST 2 SI/SDA, SCK/SCL 3 SO, PDCLK, CSYNC, BF 4 TDO 5 FID, VSYNC, HSYNC, TD0 to TD10 6 XVRST, XIICEN, XCS, TVSYNC, XTEST, OSDSW, ROSD, GOSD, BOSD, XTEST5, SYNCM, PIXCON, TDI, TMS 7 F1, SI/SDA, SCK/SCL, SYSCLK, XRST, FID, VSYNC, HSYNC, PD0 to PD15, TD8 to TD10, TCK, TRST 8 The CXD1915R supports input from 5V devices. 9 Not including analog current
-7-
CXD1915R
DAC Characteristics Item Resolution Linearity error Differential linearity error Output full-scale current Output offset voltage Output full-scale voltage Precision guaranteed output voltage range Symbol n EL ED IFS VOS VFS VOC
(AVDD = 3.3V, R = 200, VREF = 1.35V, Ta = 25C) Measurement conditions Min. Typ. 10 -2.4 -0.9 6.25 6.75 2.4 0.9 7.25 2 1.20 1.20 1.35 1.35 1.50 1.50 Max. Unit bit LSB LSB mA mV V V
-8-
CXD1915R
AC Characteristics 1. Serial port interface
fSCK tPWLSCK SCK tCSS XCS tSIS SI tSOD SO tSOH tSIH tCSH tPWHSCK
(Ta = 0 to +70C, VDD = 3.3 0.3V, Vss = 0V) Item SCK clock rate SCK pulse width Low SCK pulse width High Chip select setup time to SCK Chip select hold time to SCK Serial input setup time to SCK Serial input hold time to SCK Serial output delay time from SCK Serial output hold time from SCK Symbol fSCK Min. DC 100 100 150 150 50 10 30 3 Typ. Max. 3 Unit MHz ns ns ns ns ns ns ns ns CL = 35pF
tPWLSCK tPWHSCK tCSS tCSH tSIS tSIH tSOD tSOH
-9-
CXD1915R
2. F1
SYSCLK
tFS
tFH
F1
(Ta = 0 to +70C, VDD = 3.3 0.3V, Vss = 0V) Item F1 setup time to SYSCLK F1 hold time to SYSCLK Symbol Min. 10 0 Typ. Max. Unit ns ns
tFS tFH
3. OSDSW, ROSD, GOSD, BOSD
SYSCLK
tOS OSDSW ROSD GOSD BOSD
tOH
(Ta = 0 to +70C, VDD = 3.3 0.3V, Vss = 0V) Item OSD setup time to SYSCLK OSD hold time to SYSCLK Symbol Min. 10 0 Typ. Max. Unit ns ns
tOS tOH
- 10 -
CXD1915R
4. SYSCLK, PDCLK, BF, CSYNC, HSYNC, VSYNC, FID
fSYSCLK tPWHCLK tPWLCLK
SYSCLK tPDCLKD PDCLK VSYNC1 HSYNC1 FID1 CSYNC BF tCOD tCOH tPDCLKD
1 In master mode
(Ta = 0 to +70C, VDD = 3.3 0.3V, Vss = 0V) Item SYSCLK clock rate SYSCLK pulse width Low SYSCLK pulse width High PDCLK delay time from SYSCLK Control output delay time from SYSCLK Control output hold time from SYSCLK Symbol fSYSCLK Min. Typ. 27 11 11 20 26 3 Max. Unit MHz ns ns ns ns ns CL = 35pF
tPWLCLK tPWHCLK tPDCLKD tCOD tCOH
5. 8-bit mode (1) Pixel data interface
SYSCLK tPDS tPDH
PD0 to PD7
(Ta = 0 to +70C, VDD = 3.3 0.3V, Vss = 0V) Item Pixel data setup time to SYSCLK Pixel data hold time to SYSCLK Symbol Min. 11 0 - 11 - Typ. Max. Unit ns ns
tPDS tPDH
CXD1915R
(2) XVRST
SYSCLK
tVS
tVH
XVRST
(Ta = 0 to +70C, VDD = 3.3 0.3V, Vss = 0V) Item XVRST setup time to SYSCLK XVRST hold time to SYSCLK Symbol Min. 10 0 Typ. Max. Unit ns ns
tVS tVH
(3) HSYNC, VSYNC, FID
SYSCLK
tSYS HSYNC1 VSYNC1 FID1
tSYH
1 In slave mode
(Ta = 0 to +70C, VDD = 3.3 0.3V, Vss = 0V) Item Sync signal setup time to SYSCLK Sync signal hold time to SYSCLK Symbol Min. 10 0 Typ. Max. Unit ns ns
tSYS tSYH
- 12 -
CXD1915R
6. 16-bit mode (1) Pixel data interface
PDCLK tPDS tPDH
PD0 to PD15
(Ta = 0 to +70C, VDD = 3.3 0.3V, Vss = 0V) Item Pixel data setup time to PDCLK Pixel data hold time to PDCLK Symbol Min. 23 0 Typ. Max. Unit ns ns
tPDS tPDH
(2) XVRST
PDCLK tVS tVH
XVRST
(Ta = 0 to +70C, VDD = 3.3 0.3V, Vss = 0V) Item XVRST setup time to PDCLK XVRST hold time to PDCLK Symbol Min. 20 0 Typ. Max. Unit ns ns
tVS tVH
- 13 -
CXD1915R
(3) HSYNC, VSYNC, FID
PDCLK tSYS HSYNC1 VSYNC1 FID1 tSYH
1 In slave mode
(Ta = 0 to +70C, VDD = 3.3 0.3V, Vss = 0V) Item Sync signal setup time to PDCLK Sync signal hold time to PDCLK Symbol Min. 20 0 Typ. Max. Unit ns ns
tSYS tSYH
- 14 -
CXD1915R
Description of Functions The CXD1915R converts digital parallel data (ITU-R601 Y, Cb, Cr) into analog TV signals in NTSC (RS170A) or PAL (ITU-R624; B, G, H, I) format. The CXD1915R first receives image data in 8-bit parallel form (multiplexed Y, Cb, and Cr data), or in 16-bit parallel form (8-bit Y and 8-bit multiplexed Cb and Cr data). After demultiplexing, it converts the Cb and Cr signals into the U and V signals, respectively, interpolates 4:2:2 to 4:4:4, and then modulates the signals with the digital subcarrier inside the CXD1915R to create the chroma (C) signal. The Y and chroma (C) signals are oversampled at double speed to reduce SIN (X)/(X) roll-off, and then added to become the digital composite signal. The 10-bit DAC converts the digital composite, Y/C, U, V, and RGB signals into analog signals. 1. Pixel input format The pixel input format is selected according to the value of bit 4 (PIF MODE) of control register address 01H as shown in Table 1-1 below. When "PIF MODE" is "0", the image data (multiplexed Y, Cb, and Cr data) input from PD0 to PD7 are sampled at the rising edge of SYSCLK as shown in the chart on the following page. When "PIF MODE" is "1", the image data (PD0 to PD7: Y data, PD8 to PD15: multiplexed Cb and Cr data) input from PD0 to PD15 are sampled at the rising edge of PDCLK. PIF Mode 0 (8 bit mode) 1 (16 bit mode) PD15 to 8 NA Cb/Cr Table 1-1 Also, the pixel input data timing is determined according to bits 3 and 2 (PIX TIM) of control register address 01H as shown in Table 1-2 below. When "PIF MODE" is "0", Cb0 of the image data (Cb0, Y0, Cr0 and Y1) input from PD0 to PD7 is sampled at the respective rising edge of SYSCLK after the fall of HSYNC. (Default: Cb0 is sampled at the rising edge of the second SYSCLK after the fall of HSYNC.) When "PIF MODE" is "1", Y0 and Y1 data are input to PD0 to PD7, multiplexed Cb0 and Cr0 data are input to PD8 to PD15, and Y0 and Cb0 are sampled at the respective rising edge of PDCLK after the fall of HSYNC. (Default: Y0 and Cb0 are sampled at the rising edge of the second PDCLK after the fall of HSYNC.) PIX TIM 0 0 1 1 0 1 0 1 Timing phase #0 (default) #1 #2 #3 Table 1-2 PD7 to 0 Y/Cb/Cr Y
- 15 -
CXD1915R
Pixel Data Input Timing
1 SYSCLK
2
3
4
5
1 PDCLK HSYNC
2
3
[16-bit mode] PD0 to PD7 #0 #1 PD8 to PD15 Cb0 Cr0 Cb2 Cr2 Cb4 Cr4 Y0 Y1 Y2 Y3 Y4 Y5
Y0 #2 #3 Cb0
Y1 Cr0
Y2 Cb2
Y3 Cr2
Y4 Cb4
[8-bit mode] PD0 to PD7 #0 #1 #2 #3 Cb0 Cb0 Y0 Cb0 Y0 Cr0 Y1 Cb0 Y0 Cr0 Cb2 Y0 Cr0 Y1 Y2 Cr0 Y1 Cb2 Cr2 Y1 Cb2 Y2 Y3 Cb2 Y2 Cr2 Cb4 Y2 Cr2 Y3 Y4 Cr2 Y3 Cb4 Cr4 Y3 Cb4 Y4 Y5 Cb4 Y4 Cr4 Cb6 Y4 Cr4 Y5
PD0 PD1 : PD7
Pixel data 0 (LSB) Pixel data 1 : Pixel data 7 (MSB)
PD8 PD9 : PD15
Pixel data 0 (LSB) Pixel data 1 : Pixel data 7 (MSB)
- 16 -
CXD1915R
2. Serial interface The CXD1915R supports both the I2C bus (high-speed mode) and Sony serial interface modes. These modes can be selected by the XIICEN input pin as shown in Table 2-1 below. XIICEN SI/SDA SCK/SCL XCS/SA SO H SONY SIO Mode SI SCK XCS SO Table 2-1 I2C L Mode
SDA SCL SA High-Z
2-1. I2C bus interface The CXD1915R becomes an I2C bus slave transceiver, and supports the 7-bit slave address and the highspeed mode (400K bits/s). 2-1-1 Slave address Two kinds of slave address (88H, 8CH) can be selected by the SA signal as shown in Table 2-2 below. A6 1 A5 0 A4 0 A3 0 A2 1 A1 SA A0 0 R/W X
Table 2-2
2-1-2. Write cycle
S
Slave address
W "0"
A
start address
A
write data
A
write data
A
P
from master to slave from slave to master D7 start address D6 D5 D4 D3 D2 D1 D0
ADR[4:0]
After the slave address is supplied from the master, the data in the next transfer cycle is set up inside the start address register of this IC as the start address of the control register. In subsequent cycles, the data supplied from the master is written in the addresses indicated by the control register address. The set control register address is automatically incremented with the transfer completion of each byte of data. - 17 -
CXD1915R
2-1-3. Read cycle S Slave address R "1" from master to slave from slave to master A read address A read data A P
After the slave address is supplied from the master, subsequent cycles change immediately to read cycles and only the ID code (address 0CH, 0DH) is read out. During the read cycle, the start address is automatically set to 0CH. Note: In Sony SIO mode, addresses from 00H to 0DH can be read out. 2-1-4. Handling of general call address (00H) The general call address is ignored and there is no ACK response.
- 18 -
CXD1915R
2-2. Sony serial interface The Sony serial interface uses the SCK, XCS, SI and SO signals. The serial interface is active when the XCS signal is Low and transmits and receives signals to and from the host. The first byte after the XCS signal becomes Low is set up as a serial control command. Its data includes a control register address and read/write mode information for the interface. (See 2-2-1. Serial control command format.) The control register address is automatically incremented with the transfer completion of each byte of data. In write mode, the SI signal of the serial input data is sampled at the rising edge of the SCK signal. In read mode, the register value is read out as the SO signal of the serial output data at the falling edge of the SCK signal, and is variable. In this case, the SI signal of the serial input data is ignored. Serial Interface Timing
SCK XCS SI D0 LSB SO D1 D2 D3 D4 D5 D6 D7 MSB D0 LSB D0 D1 D1 D2 D3 D4 D5 D6 D7 MSB D5 D6 D7
Serial Control Command
Serial Data D2 D3 D4
Serial Interface Sequence
SCK XCS SI Internal address 00H FFH 00H 11H 01H CEH 02H
Control register address set Control Register Address 00H 01H 02H
Control register address auto-increment Control Register Data FFH 11H CEH
Control register address auto-increment
2-2-1. Serial control command format D7 WR WR: D6 D5 D4 D3 D2 D1 D0
ADR[4:0]
Read/write mode When this bit is "1": The serial interface is write mode, and the SI signal of the serial input data is written in the register. When this bit is "0": The serial interface is read mode, and the register value is read out as the SO signal of the serial output data. ADR[4:0]: Control register address setting (Initial value of the address) - 19 -
CXD1915R
3. XVRST, F1 The XVRST and F1 signals are used to synchronize with the external V sync. The XVRST and F1 signals are sampled at the rising edge of SYSCLK, and the F1 signal is sampled when XVRST is Low. When F1 is High, the internal sync generator is reset to the 1st field, and when F1 is Low, it is reset to the 2nd field. When XVRST is set to High, the digital sync generator starts operation, and the sequence of the 1st or 2nd field starts.
[8-bit mode] XVRST Timing (1st Field)
SYSCLK
XVRST
F1 "H" VSYNC FID HSYNC Start of 1st field (NTSC: 4H) (PAL: 1H)
XVRST Timing (2nd Field)
SYSCLK
XVRST
F1 "L" Start of 2nd field (NTSC: 266H) (PAL: 313H)
VSYNC FID
1/2H HSYNC
- 20 -
CXD1915R
[16-bit mode] XVRST Timing (1st Field)
PDCLK
XVRST
F1 "H" VSYNC FID HSYNC Start of 1st field (NTSC: 4H) (PAL: 1H)
XVRST Timing (2nd Field)
PDCLK
XVRST
F1 "L" Start of 2nd field (NTSC: 266H) (PAL: 313H)
VSYNC FID
1/2H HSYNC
- 21 -
CXD1915R
4. External synchronization The CXD1915R can select master or slave operation using the SYNCM input pin. When the SYNCM signal is Low, the CXD1915R is set to slave mode, and synchronizes to an external source using the HSYNC, VSYNC and FID I/O pin inputs. The signal combinations used for external synchronization are set by bit 7 (SSEL) of control register 03H. Register setting 1 0 (default) HSYNC Used Used VSYNC Ignored Used FID Used Ignored
4-1. V synchronization 4-1-1. When SSEL = 0 (default), the CXD1915R identifies the data as the 1st field when the falling edges of the HSYNC and VSYNC signals match, or as the 2nd field when the falling edges do not match. The CXD1915R performs synchronization reset only during the 1st field.
VSYNC
HSYNC
CPSYNC
4-1-2. When SSEL = 1, operation is reset to the 1st field at the falling edge of the FID signal. In this case, set bit 7 (FIDS) of control register 00H to High (default).
FID
HSYNC
CPSYNC
4-2. H synchronization The horizontal line is reset by detecting the falling edge of the HSYNC signal. Be sure to perform reset at the precise period. - 22 -
CXD1915R
5. Closed caption The CXD1915R supports closed caption encoding. ASCII data for closed captions are encoded in line 21 and line 284 by adding a parity bit to every ASCII data set up in control registers 04H, 05H (data #1 and #2 for line 21) and 06H, 07H (data #1 and #2 for line 284). The control registers (04H to 07H) are double-buffered and ASCII data, which are set up by the serial interface, are synchronized with the VSYNC signal. Automatic reset on/off can be selected for ASCII data which has been synchronized with VSYNC by changing the setting of bit 5 (CCRST) of control register address 03H. When CCRST = "1", the control registers (04H, 05H or 06H, 07H) are automatically reset in sync with the rise of the next VSYNC. When CCRST = "0" (default), the control registers (04H, 05H or 06H, 07H) are not reset, and the data set last is held. Closed Caption Data Renewal Timing
When CCRST = "1" Field VSYNC Control registers 04H and 05H set SI/SDA Data 21H Front-end buffer Data 21H Rear-end buffer Data 284H Front-end buffer Data 284H Rear-end buffer Field VSYNC Control registers 06H and 07H set SI/SDA Data 284H Front-end buffer Data 284H Rear-end buffer Data 21H Front-end buffer Data 21H Rear-end buffer DATA A OLD DATA OLD DATA DATA RESET (7'h00) DATA A (7'h00) NEW DATA NEW DATA (7'h00) NEW DATA DATA A OLD DATA OLD DATA DATA RESET (7'h00) DATA A (7'h00) NEW DATA NEW DATA (7'h00) NEW DATA Field 4 Field 1
Field 1
Field 2
- 23 -
CXD1915R
When CCRST = "0" Field VSYNC Control registers 04H and 05H set SI/SDA Data 21H Front-end buffer Data 21H Rear-end buffer Data 284H Front-end buffer Data 284H Rear-end buffer Field VSYNC Control registers 06H and 07H set SI/SDA Data 284H Front-end buffer Data 284H Rear-end buffer Data 21H Front-end buffer Data 21H Rear-end buffer OLD DATA OLD DATA DATA A DATA A NEW DATA NEW DATA NEW DATA OLD DATA OLD DATA DATA A DATA A NEW DATA NEW DATA NEW DATA Field 4 Field 1
Field 1
Field 2
Double Buffer for Closed Caption
SI/SDA 04H
VSYNC
Load
ASCII data #1
Closed Caption Signal Waveform
HSYNC Color Burst Clock Run-In Start Bits ASCII Data #1 ASCII Data #2
S1 S2 S3 b0 b1 b2 b3 b4 b5 b6 P1 b0 b1 b2 b3 b4 b5 b6 P2
50 IRE
- 24 -
CXD1915R
6. VBID (Video ID) The CXD1915R supports encoding of Video ID (Provisional Standard EIAJ CPX-1204) to discriminate the aspect ratio. VBID is 14-bit data as shown in Table 6-1, and becomes 20-bit data with the addition of 6-bit CRCC. These data are superimposed on lines 20 and 283 during the vertical blanking period of NTSC video signals and output. The data setting in Table 6-1 below is done by writing data in control registers (08H and 09H) via the serial interface. These control registers (08H and 09H) are double-buffered, and the VBID data are renewed in sync with the VSYNC signal. bit-No. 1 2 3 4 5 6 4-bit width 4-bit width Contents "1" A Word 0 B Word 1 Word 2 Transmission aspect ratio Image display format Undefined Full-mode (16:9) Letter-box 4:3 Normal "0"
Identification information about video and other signals (audio signals, etc.) incidental to images which are transmitted simultaneously Identification signal incidental to Word 0 Identification signal and information incidental to Word 0 Table 6-1
Double Buffer for VBID
SI
08H
VSYNC
Load
Word 0
VBID Data Renewal Timing
VSYNC Control register 08H set SI NEW DATA
Data #1
OLD DATA
NEW DATA
- 25 -
CXD1915R
VBID Code Allocation The VBID data are composed of Word 0 = 6 bits (Word 0-A = 3 bits and Word 0-B = 3 bits), Word 1 = 4 bits, Word 2 = 4 bits, and CRCC = 6 bits. bit 0 *** Data *** bit 20
0-A Word 0 6 bits VBID Signal Waveform
0-B
Word 1 4 bits
Word 2 4 bits
CRCC 6 bits
Ref.
bit 1 bit 2 bit 3
***
bit 20
2.235s 20ns
11.2s 0.6s
49.1s 0.5s 1H
- 26 -
CXD1915R
7. WSS (Widescreen Signaling) The CXD1915R supports WSS encoding to discriminate the aspect ratio. WSS is 14-bit data as shown in Table 7-1. These data are superimposed on line 23 during the vertical blanking period of PAL video signals and output. The data setting in Table 7-1 below is done by writing data in control registers (0AH and 0BH) via the serial interface. These control registers (0AH and 0BH) are double-buffered, and the WSS data are renewed in sync with the VSYNC signal. Group 1 Aspect ratio information (4 bits) b0 to b3 0001 1000 0100 1101 0010 1011 0111 1110 Normal Letter-box Letter-box Letter-box Letter-box Letter-box > Full-mode Full-mode 14:9 Center 14:9 Top 16:9 Center 16:9 Top 16:9 Center 14:9 16:9 Group 2 PAL plus related information (4 bits) b4 to b7
bit 4 Camera/Film mode bits 5 to 7 Reserved (Color plus) (Helper) (BasebandHelper)
b3 is odd parity. Group 3 Subtitle information (3 bits) b8 to b10 Bit 8 Bits 9, 10 00 10 01 11 TeleText subtitle enable/disable No subtitle Subtitle inside screen Subtitle in black portion Reserved Reserved Group 4 Undefined (3 bits) b11 to b13
Table 7-1 Double Buffer for WSS
SI 0AH
VSYNC
Load
Group1, 2
WSS Data Renewal Timing
VSYNC Control register 0AH set SI NEW DATA
Data #1
OLD DATA
NEW DATA
- 27 -
CXD1915R
WSS Signal Waveform
bit 0 bit 1 bit 2 649
***
bit 13 71.4 IRE
RUN Start -IN Code
256
0 IRE
20 11.03s 10.67s 16.59s
8. RGB/YUV output The CXD1915R has an RGB/YUV output function. RGB and YUV can be switched by setting bit 2 (RGB_UV) of control register address 03H. Also, the UV level can be selected from BetaCam or SMPTE by setting bit 0 (BTCM) of address 03H. During RGB output, when bit 1 (GSYNC) of control register address 03H is "1", the sync signal is added to the G signal and output; when bit 1 (GSYNC) is "0", the sync signal is not added.
9. Support of interlace/non-interlace modes The CXD1915R can be switched to the interlace and non-interlace modes by varying the setting of bit 1 (INTERLS) of control register address 01H. During the non-interlace mode, the 1st field is repeatedly output. Register setting value INTERLS 0 (non-interlace) 1 (interlace) Number of lines/field NTSC 262 262.5 PAL 312 312.5
- 28 -
CXD1915R
10. Support of NTSC, PAL, MPAL and 4.43NTSC The CXD1915R can convert to NTSC, PAL, MPAL and 4.43NTSC analog TV signals by setting bits 2, 1 and 0 (ENC MODE) of control register address 00H. Register setting value ENC MODE 0 0 0 1 0 0 1 0 0 1 1 1 Encoding mode PAL NTSC MPAL 4.43NTSC Number of lines/field 625/50 525/60 525/60 525/60 Subcarrier line phase difference 135 180 135 180 Subcarrier frequency [MHz] 4.4336 (10 1cycles) 3.5795 (9 1cycles) 3.5756 (9 1cycles) 4.4336
11. OSD The CXD1915R can be switched to OSD mode by setting bit 6 (OSDEN) of control register address 02H. At this time, if OSDSW (Pin 67) = 1, the OSD input pin is enabled. Also, the luminance level can be selected from the four levels of 25%, 50%, 75% and 100% by varying the setting of bits 5 and 4 (Y_LEV) of control register address 02H. This allows 29-color (7 colors x 4 levels + black) OSD output. (Up to 8 colors can be displayed at once.) Color White Yellow Cyan Green Magenta Red Blue Black ROSD (Pin 68) 1 1 0 0 1 1 0 0 GOSD (Pin 69) 1 1 1 1 0 0 0 0 BOSD (Pin 70) 1 0 1 0 1 0 1 0
12. Support of square pixels The CXD1915R can be switched to support square pixels by setting bit 4 (SQPIX) of control register address 00H. MPAL and 4.43NTSC cannot be used in square pixel mode. Register setting value SQPIX 0 1 Mode Normal mode Square pixel mode Pixel clock frequency [MHz] NTSC 13.5 12.272727 PAL 13.5 14.75
13. On-chip 100% color bar generator The CXD1915R can display an ITU_R100% color bar from its internal generator by setting bit 7 (CBAR) of control register address 02H. - 29 -
CXD1915R
14. ITU-656EAV decoding The CXD1915R decodes the EAV of the ITU-656 1st field and performs internal synchronization every 4 fields for NTSC or every 8 fields for PAL by setting bit 3 (D1 MODE) of control register address 03H.
- 30 -
Signal Waveform of NTSC Vertical Blanking Period (Interlace mode)
Fields 1 and 3 Vertical blanking Pre-equalization 3H Vertical sync 3H Post-equalization 3H
524
525
1
2
3
4
5
6
7
8
9
10
11
19
20
21
22
23
HSYNC
VSYNC
- 31 -
Fields 2 and 4 263 264 265 266 267 268 269 270 271 272 273 274
FID
261
262
282
283
284
285
HSYNC
VSYNC
FID
CXD1915R
Signal Waveform of PAL Vertical Blanking Period (Interlace mode)
Fields 1 and 3
(2) (4) (4) (3) 2.5H 2.5H 2.5H (1) (3)
620 623 3
621
622
624
625
1
2
4
5
6
7
8
20
21
22
23
24
HSYNC
VSYNC
FID
- 32 -
Fields 2 and 4 (3) (2) (4) (2) 310 311 312 313 314 315 316 317 318 319 320 321 Field 1 Field 2 Field 3 Field 4
(1) (3)
308
309
333
334
335
336
HSYNC
VSYNC
FID
Meander gate
CXD1915R
Signal Waveform of NTSC Vertical Blanking Period (Non-interlace mode)
Field 11
3H
3H
3H
523
524
1
2
3
4
5
6
7
8
9
10
11
19
20
21
22
23
HSYNC
VSYNC
FID
- 33 -
Field 21 263 264 265 266 267 268 269 270 271 272 273
261
262
291
282
283
284
285
HSYNC
VSYNC
FID
1 No differentiation is made between Fields 1 and 2 to facilitate the frame description.
CXD1915R
Signal Waveform of PAL Vertical Blanking Period (Non-interlace mode)
Field 11
2H
2.5H
2.5H
620
621
622
623
624
1
2
3
4
5
6
7
8
20
21
22
23
24
HSYNC
VSYNC
FID Field 21
- 34 -
2H 2.5H 2.5H 310 311 312 313 314 315 316 317 318 319 320
308
309
332
333
334
335
336
HSYNC
VSYNC
FID CXD1915R 1 No differentiation is made between Fields 1 and 2 to facilitate the frame description.
CXD1915R
Sync Signal Timing
0.148s 0.148s
2.3s
29.5s
27.1s 1/2H 63.555s
4.67s
NTSC Equalizing Pulse and Sync Pulse Signal Waveform
0.296s
0.296s
2.37s
29.63s
27.3s 1/2H 64s
4.67s
PAL Equalizing Pulse and Sync Pulse Signal Waveform
- 35 -
CXD1915R
Control Register Map BIT Function Selection #1 7 Address 00H ENC MODE FIDS 6 MASK EN 5 PIX EN 4 SQPIX 3 SET UP 2 1 ENC MODE 0 R/W
Encoding mode 000: PAL encoding mode 001: NTSC encoding mode (Default) 010: Inhibit 011: MPAL encoding mode 100: Inhibit 101: 4.43NTSC encoding mode 110: Inhibit 111: Inhibit Setup enable 0: No setup level, black level = blanking level 1: 7.5 IRE setup level insertion (Default) Square pixel 0: Disable square pixel mode (13.5MHz) (Default) 1: Enable square pixel mode Pixel data enable PIXCON input pin = High PIXCON input pin = Low
SET UP
SQPIX
PIX EN
0: Disable input pixel data 1: Enable input pixel data (Default) 0: Disable input pixel data (Default) 1: Enable input pixel data
MASK EN
Mask enable 0: Pixel data through during vertical blanking period 1: Pixel data reject during vertical blanking period (Default) FID polarity select SYNCM input pin = High 0: 1st field High, 2nd field Low 1: 1st field Low, 2nd field High (Default) SYNCM input pin = Low Fixed to "1".
FIDS
- 36 -
CXD1915R
BIT Function Selection #2 7 Address 01H FREERUN 6 DAC MODE 5 4 PIF MODE 3 PIX TIM 2 1 INTERLS 0 FREE RUN R/W
Free running 0: Reset applied every 4 fields during NTSC or every 8 fields during PAL and MPAL (Default) 1: No SCH timing reset Interlace mode switching 0: Non-interlace mode 1: Interlace mode (Default) Pixel input timing 00: #0 (Default) 01: #1 10: #2 11: #3 Pixel input format 0: 8-bit mode, multiplexed Y, Cb, Cr (4:2:2) (Default) 1: 16-bit mode, Y and multiplexed Cb, Cr (4:2:2) DAC output activity 000: Non-active 001: CP-Out active 010: Inhibit 011: Video signal (Y, C, CP) -Out active (Default) 100: Inhibit 101: R, G, B-Out and CP-Out active 110: Inhibit 111: All outputs active
INTERLS
PIX TIM
PIF MODE
DAC MODE
- 37 -
CXD1915R
BIT Function Selection #3 7 Address 02H CC MODE CBAR 6 OSDEN 5 Y_LEV 4 3 VBID 2 WSS 1 CC Mode 0 R/W
Closed caption encoding mode 00: Disable closed caption encoding (Default) 01: Enable encoding in 1st field (Line 21) 10: Enable encoding in 2nd field (Line 284) 11: Enable encoding in both fields WSS encoding enable 0: Disable WSS encoding (Default) 1: Enable WSS encoding VBID encoding mode 0: Disable VBID encoding (Default) 1: Enable VBID encoding OSD luminance level select 00: 100% (Default) 01: 25% 10: 50% 11: 75% OSD enable 0: Disable OSD (Default) 1: Enable OSD Color bar enable 0: Disable on-chip color bar output (Default) 1: Enable on-chip color bar output (ITU_R100% color bar)
WSS
VBID
Y_LEV
OSDEN
CBAR
- 38 -
CXD1915R
BIT Function Selection #4 7 Address 03H BTCM SSEL 6 BF 5 CCRST 4 3 D1 MODE 2 RGB_UV 1 GSYNC 0 BTCM R/W
UV output level control 0: SMPTE 1: BetaCam (Default) G-on SYNC enable 0: Disable (Default) 1: Enable RGB/YUV output mode switching 0: YUV (Default) 1: RGB ITU-R656 EAV decoding 0: Disable ITU-R656 EAV decoding (Default) 1: Enable ITU-R656 EAV decoding Closed caption character reset enable 0: Disable (Default) 1: Enable Burst flag enable 0: Disable burst flag 1: Enable burst flag (Default) Sync select Selects the sync signal used during slave mode. HSYNC VSYNC FID 0: Used Used Ignored (Default) 1: Used Ignored Used
GSYNC
RGB_UV
D1 MODE
CCRST
BF
SSEL
- 39 -
CXD1915R
BIT Closed Caption Character #1 (Line 21H) 7 Address 04H 6 5 4 3 2 1 0 R/W
ASCII Data #1
(Default: 0H)
Closed Caption Character #2 (Line 21H) 7 Address 05H 6 5 4 3 2 1 0 R/W
ASCII Data #2
(Default: 0H)
Closed Caption Character #1 (Line 284H) 7 Address 06H 6 5 4 3 2 1 0 R/W
ASCII Data #1
(Default: 0H)
Closed Caption Character #2 (Line 284H) 7 Address 07H 6 5 4 3 2 1 0 R/W
ASCII Data #2
(Default: 0H)
VBID #1 7 Address 08H 6 5 4 Word 0-B 3 Word 0 Word 0-A 2 1 0 R/W
VBID #2 7 Address 09H 6 Word 2 5 4 3 2 Word 1 1 0 R/W
WSS #1 7 Address 0AH bit 7 6 Group 2 bit 6 5 bit 5 4 bit 4 3 bit 3 2 bit 2 1 Group 1 bit 1 0 bit 0 R/W
WSS #2 7 Address 0BH 6 5 bit 13 4 Group 4 bit 12 - 40 - 3 bit 11 2 bit 10 1 Group 3 bit 9 0 bit 8 R/W
CXD1915R
BIT Device ID #1 7 Address 0CH ID code 6 5 4 ID Code Identification: 15H 3 2 1 0 RO
(Lower) 15H
Device ID #2 7 Address 0DH ID code 6 5 4 ID Code Identification: 19H 3 2 1 0 RO
(Upper) 19H
- 41 -
CXD1915R
Video Signal Timing (NTSC, 7.5 IRE Setup)
MAGENTA
YELLOW
GREEN
806
806 748 655 597
BLACK
WHITE
CYAN
BLUE
RED
WHITE LEVEL
100 IRE 7.5 IRE 256 40 IRE 36
506 448 355 297 BLACK LEVEL BLANK LEVEL
SYNC LEVEL
NTSC Y (luminance) signal output waveform 7.5 IRE setup
MAGENTA (299)
YELLOW (227)
GREEN (299)
CYAN (320)
BLUE (227)
RED (320)
832
622 20 IRE 512 402 COLOR BURST BLANK LEVEL
192
NTSC C (chroma) signal output waveform 7.5 IRE setup
WHITE
- 42 -
BLACK
CXD1915R
Video Signal Timing (NTSC, No Setup)
MAGENTA
YELLOW
GREEN
806
806 744 643 580
BLACK
WHITE
CYAN
BLUE
RED
WHITE LEVEL
100 IRE
482 419 318 BLANK LEVEL
256 40 IRE 36
SYNC LEVEL
NTSC Y (luminance) signal output waveform
YELLOW (245)
GREEN (324)
CYAN (347)
MAGENTA (324)
BLUE (245)
RED (347)
859
622 20 IRE 512 402 COLOR BURST BLANK LEVEL
165
NTSC C (chroma) signal output waveform
WHITE
- 43 -
BLACK
CXD1915R
Video Signal Timing (PAL)
MAGENTA
YELLOW
GREEN
806
806 744 643 580
BLACK
WHITE
CYAN
BLUE
RED
WHITE LEVEL
100 IRE
482 419 318 BLANK LEVEL
256 43 IRE 20
SYNC LEVEL
PAL Y (luminance) signal output waveform
MAGENTA (324)
YELLOW (245)
GREEN (324)
CYAN (347)
BLUE (245)
RED (347)
859
630 21.5 IRE 512 394 COLOR BURST BLANK LEVEL
165
PAL C (chroma) signal output waveform
WHITE
- 44 -
BLACK
CXD1915R
RGB Signal Output Waveform
806 100 IRE 256
806
806
257
257
805
805
256
256
BLACK WHITE LEVEL BLANK LEVEL 256 BLACK WHITE LEVEL BLANK LEVEL WHITE LEVEL BLANK LEVEL SYNC LEVEL WHITE LEVEL BLANK LEVEL SYNC LEVEL 256 BLACK WHITE LEVEL BLANK LEVEL
WHITE
CYAN
WHITE
CYAN
806 100 IRE 256 During G-on SYNC (NTSC) 806 100 IRE 256 40 IRE 36 During G-on SYNC (PAL) 806 100 IRE 256 43 IRE 20
806
807
806
806
256
256
256
WHITE
CYAN
806 100 IRE 256
806
257
808
259
803
256
806
- 45 -
BLUE
B signal
MAGENTA
YELLOW
GREEN
RED
BLUE
G signal
MAGENTA
YELLOW
GREEN
RED
BLUE
R signal
MAGENTA
YELLOW
GREEN
RED
CXD1915R
UV Output Level Color Difference (U) Signal
SMPTE LEVEL MAGENTA YELLOW GREEN BLACK WHITE Beta Cam LEVEL MAGENTA YELLOW GREEN BLACK WHITE
CYAN
CYAN
BLUE
782 690 603 643 768
901
512
512
421 334 242 NTSC 123 256
381
NTSC, No setup
871 750 633
512
391 274 153 NTSC, Setup
787 693 605 605 693
787
512
512
419 331 237 PAL 237 331
419
PAL
- 46 -
BLUE
RED
RED
CXD1915R
Color Difference (V) Signal
SMPTE LEVEL MAGENTA YELLOW GREEN BLACK WHITE Beta Cam LEVEL MAGENTA YELLOW GREEN BLACK WHITE
CYAN
CYAN
BLUE
782 738 838
901
555 512 469 512
574
450
286 242 NTSC 123
186
NTSC, No setup
871 813
570 512 453
211 153 NTSC, Setup
787 742 742
787
556 512 468 512
556
468
282 237 PAL 237
282
PAL
- 47 -
BLUE
RED
RED
CXD1915R
Internal Filter Characteristics
Interpolation Filter Characteristic
0
-10 Attenuation [dB]
-20
-30
-40
-50
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
Frequency [MHz]
Chrominance Filter Characteristic
0
-20 Attenuation [dB]
-40
-60
-80
-100
0
1
2
3
4
5
6
7
8
9
10
Frequency [MHz]
- 48 -
CXD1915R
DAC Application Circuit
CXD1915R
AVDD VG 0.1F VREF 3.2k IREF AVSS 1k
CP-OUT Y-OUT C-OUT 0.1F VB G/Y-OUT B/U-OUT R/V-OUT
Buff AMP LPF 75 200
VSS
Application Circuit
CXD1915R (Video encoder)
MPEG decoder
Y C FID HSYNC VSYNC DCLK CLK
8 8
PD0 to PD7 PD8 to PD15 FID HSYNC VSYNC
13.5MHz
PDCLK SYSCLK
27MHz
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
- 49 -
CXD1915R
Package Outline
Unit: mm
80PIN LQFP (PLASTIC)
14.0 0.2 60 61 12.0 0.1 41 40
A
80 1 + 0.08 0.18 - 0.03 20
21 (0.22)
0.5
0.13 M
+ 0.2 1.5 - 0.1
+ 0.05 0.127 - 0.02 0.1
0.1 0.1
0 to 10
0.5 0.2
NOTE: Dimension "" does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-80P-L01 LQFP080-P-1212 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42 ALLOY 0.5g
- 50 -
0.5 0.2
(13.0)

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